The present invention relates to electronic circuitry and more particularly to systems and methods for testing and/or programming.
The complexity of the electronic circuitry on printed circuit boards (PCBs) continues to increase. A single PCB may have a very large number of integrated circuits. With continued progress in large scale integration, many of these integrated circuits may have tens of millions or even hundreds of millions of transistors. As the amount of circuitry on a single integrated circuit increases, so does the number of input/output pins. There is also a very high density of interconnections among the integrated circuits.
With the increased complexity comes a very great challenge in testing the PCBs and debugging faults in an efficient manner. Also, many of the devices on the board may be programmable logic devices (PLDs) such as PROMs, FPGAs, CPLDs, etc. Thus, the configuration of the PCB may involve downloading a very large amount of programming information into multiple programmable devices.
To reduce the burden of testing PCBs, integrated circuit vendors often incorporate extra hardware within their integrated circuit to facilitate testing and debugging. IEEE standard 1149.1, also referred to as JTAG or Boundary Scan, specifies a serial interface in combination with an internal state machine to facilitate external testing of compliant devices. To minimize the need for numerous test connections to the PCB, the serial interfaces of multiple devices may be connected together in what is referred to as a scan chain. The IEEE standard 1149.1 may also be used for external programming of devices on a PCB. It is also known to use JTAG to program a programmable device from a source internal to the PCB.
What is needed are systems and methods that provide flexibility in switching between external JTAG testing and/or programming and internal JTAG programming.